1. Field of the Invention
This invention relates to semiconductor processes and more particularly to a high speed, high yield CMOS/SOS process for production of CMOS/SOS devices.
2. Description of the Prior Art
As the semiconductor industry moves into faster operations, lower cost utilizations, it becomes imperative that better processes and better materials or combinations thereof be provided. One of the improved utilization of materials is the use of sapphire as a substrate. In using sapphire substrates a new technology referred to as silicon-on-sapphire (SOS) has been developed. In addition, it has been established that complementary metal-oxide-semiconductors (CMOS) have distinct advantages. That is, opposite conductivity type devices can be established in a single unit during essentially a single process.
It has been further established that a combination of these two technologies to produce CMOS/SOS devices would incorporate the advantages of each of the concepts together.
The elusive factor, however, has been to establish a CMOS/SOS process for use in production applications which would yield low resistance n-type silicon regions where desired, while providing high yield and high speed production.
In attempting to provide the low resistance n-type regions, it has been determined that it is desirable to use a phosphorous furnace deposition to provide n-type doping of the silicon. However, undesirable interactions occur between the phosphorous and the sapphire which result in the formation of an intermediate phosphorous-sapphire compound. This compound is undesirable insofar as it lifts off the surface of the sapphire and deposits over the rest of the wafer in such a manner that it cannot be readily removed. Also, a possible phosphorous-rich layer exists on the sapphire throughout the remainder of the processing. Also, erosion of the sapphire results which is especially harmful adjacent the p-type islands wherein the compound causes an undercutting and therefore a counter doping of the thermally oxidized p-type islands.
Moreover, during the furnace deposition of phosphorous, it has been determined that there is a likelihood of phosphorous penetration through the thermal oxide which has been grown over the p-type islands. This penetration occurs through the portion of the oxide nearest the sapphire where the oxide is the thinnest due to the limited amount of silicon available for formation of thermal oxide. Again, this penetration by the phosphorous causes counter doping of the p-type islands near the sapphire interface.